1. Field of the Invention
The present invention generally relates to a method for manufacturing a circuit board, and more specifically to a method for manufacturing a circuit board comprising a sputtering process, a chemical plating process and an electroplating process sequentially performed to form a first metal layer on a substrate, a second metal layer on the first metal layer and a third metal layer on the second metal layer, respectively, and further comprising a circuit etching process to form an electrical circuit with fine line width/pitch by etching the first and second metal layers.
2. The Prior Arts
Recently, as the technology of the VLSI (very large scale integrated circuit) made great progress, the connection circuit has become much smaller. For example, in the 22 nm semiconductor technology, both chip density and ability of signal processing are increasingly enhanced. As a result, the line width/pitch of the connection circuit needs smaller size, and the current equipments and processes for mass production encounter tough challenge. Additionally, to further increase package density, the chips are usually stacked together and then processed by the three dimensional package. At this time, the line width/pitch of the circuit substrate needs to be reduced to 30-50 μm from 100 μm. As for the requirements by the current manufactures for increasingly reducing the line width/pitch, the surface structure of the copper layer for the circuit pattern should meet more strict requirements. Generally, roughness Rz of the copper layer in the printed circuit board (PCB) is 5-7 μm, and roughness Rz of the substrate is less than 5 μm. However, for the line width/pitch about 10-20 μm, roughness Rz of the copper layer should be about 2 μm, or otherwise the circuit pattern is easily distorted to cause the circuit board to fail to normal function. Sometimes, the circuit pattern is short circuited due to some remaining copper such that high precision and reliability for electrical connection can be implemented.
In the prior arts, the semi additive process (SAP) is usually used to manufacture the electrical circuit pattern with the line width/pitch less than 50 μm. For the line width/pitch less than 25 μm, The SAP needs to use ABF resin provided by Ajinomoto Fine-Techno Co., Inc. as the insulation material, or a PCF (primer coated copper foil) and a semi solid sheet (called Prepreg) provided by Mitsubishi Gas Chemical Company, INC., Ltd. for the pressing process. As for the PCF, one rough surface of the copper foil is first covered with a resin layer with a thickness of 2-3 μm and then processed by semi solidification, and the semi solid sheet and the copper foil are pressed together. The copper foil is removed and the surface of the resin layer has specific roughness. Thus, the chemical copper plating process (or called the electroless plating process) can form the chemical plated copper layer with strong adhesion on the rough surface of the resin layer, thereby manufacturing more precise circuit pattern.
As an example for SAP using the PCF, the specific implementation includes first pressing the PCF onto the inner circuit layer, removing the copper on the PCF to remain the resin with highly specific surface feature, and performing the chemical plating process to form the circuit pattern layer with fine line width/pitch.
However, one of the shortcomings for the above methods in the prior arts is that the remaining resin is not stable after the PCF is removed such that the circuit pattern layer formed by the chemical plating process is easy to break, peel off due to weak adhesion. It is thus difficult to prevent the portion of the circuit patter layer filling up the blind holes as connection plug with a vertical shape from being shifted or distorted. As a result, the electrical property and reliability of the electrical circuit of the circuit board are adversely affected.
Therefore, it is greatly needed to provide a new method for manufacturing a circuit board, which generally comprises a sputtering process for forming a first metal layer on a substrate, a chemical plating process for forming a second metal layer on the first metal layer, an electroplating process for forming a third metal layer on the second metal layer, and a circuit etching process for forming an electrical circuit with fine line width/pitch by etching the first and second metal layers, thereby overcoming the above problems in the prior arts.